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1. Consider two different implementations, MI and M2, of the same instruction set. There are three classes of instructions (A, B, and C) in the instruction set. M1 has a clock rate of 4 GHz and M2 has a clock rate of 2 GHz. The CPI for each instruction class on M1 and M2 is given in the following table: Class CPI on M1 CPI on M2 C1 Usage A 1 2 40% B 3 2 50% C 4 2 10% C2 Usage 30% 30% 40% The table above also contains a summary of the usage of the instruction classes generated by two different compilers, C1 and C2. Assume for any given program that compiler C1 generates 10% more instructions than compiler C2. Which implementation and compiler combination gives the best performance?

1. Consider two different implementations, MI and M2, of the same instruction set. There are three classes of instructions (A, B, and C) in the instruction set. M1 has a clock rate of 4 GHz and M2 has a clock rate of 2 GHz. The CPI for each instruction class on M1 and M2 is given in the following table: Class CPI on M1 CPI on M2 C1 Usage A 1 2 40% B 3 2 50% C 4 2 10% C2 Usage 30% 30% 40% The table above also contains a summary of the usage of the instruction classes generated by two different compilers, C1 and C2. Assume for any given program that compiler C1 generates 10% more instructions than compiler C2. Which implementation and compiler combination gives the best performance?

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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1. Consider two different implementations, M1 and M2, of the same instruction set. There are three classes of instructions (A, B, and C) in the instruction set. M1 has a clock rate of 4 GHz and M2 has a clock rate of 2 GHz. The CPI for each instruction class on M1 and M2 is given in the following table: Instruction Class ALU The table above also contains a summary of the usage of the instruction classes generated by two different compilers, C1 and C2. Assume for any given program that compiler C1 generates 10% more instructions than compiler C2. Which implementation and compiler combination gives the best performance? Load Class CPI on M1 A 1 B 3 C 4 Compare the performance of a single-cycle processor and a multi-cycle processor. The delay times are as follows: - Instruction memory access time = 500 ps, Data memory access time = 500 ps, Instruction Decode and Register read = 300 ps Register write = 100 ps, ALU delay = 300 ps - Ignore the other delays in the multiplexers, wires, etc. Assume the following instruction mix: 40% ALU, 20% load, 10% store, 20% branch, and 10% jump. a) Compute the delay for each instruction class and the clock cycle for the single cycle Store Branch Jump CPI on M2 C1 Usage 2 2 2 Instruction Memory Decode and Register Read 40% 50% 10% ALU Data Memory C2 Usage 30% 30% 40% Write Back b) Compute the clock cycle and the average CPI for the multi-cycle processor Total Delay
Transcribed Image Text:1. Consider two different implementations, M1 and M2, of the same instruction set. There are three classes of instructions (A, B, and C) in the instruction set. M1 has a clock rate of 4 GHz and M2 has a clock rate of 2 GHz. The CPI for each instruction class on M1 and M2 is given in the following table: Instruction Class ALU The table above also contains a summary of the usage of the instruction classes generated by two different compilers, C1 and C2. Assume for any given program that compiler C1 generates 10% more instructions than compiler C2. Which implementation and compiler combination gives the best performance? Load Class CPI on M1 A 1 B 3 C 4 Compare the performance of a single-cycle processor and a multi-cycle processor. The delay times are as follows: - Instruction memory access time = 500 ps, Data memory access time = 500 ps, Instruction Decode and Register read = 300 ps Register write = 100 ps, ALU delay = 300 ps - Ignore the other delays in the multiplexers, wires, etc. Assume the following instruction mix: 40% ALU, 20% load, 10% store, 20% branch, and 10% jump. a) Compute the delay for each instruction class and the clock cycle for the single cycle Store Branch Jump CPI on M2 C1 Usage 2 2 2 Instruction Memory Decode and Register Read 40% 50% 10% ALU Data Memory C2 Usage 30% 30% 40% Write Back b) Compute the clock cycle and the average CPI for the multi-cycle processor Total Delay
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