Realize Z =A[BC' + D + E(F' + GH)] using NOR gates. Add inverters if necessary.
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- Sometimes "bubbles" are used to indicate inverters on the input lines to a gate. What are the equivalent gates for those shown in the figure below? Hint - use DeMorgan's Law. A B C=A+B (a) D F=DE E (b)(b) For a gated S-R latch. determine the Q output for the inputs in the following Figure. Show it in proper relation to the enable input, also draw the input waveforms on your answer script. Assume that Q starts LOW. EN S R Minimize the combinational logic circuit in the following figure using Karnaugh's map only. Inverters for the complemented variables are not shown. Q2.Consider a family of logic gates that operate under the static discipline with the following voltage thresholds: VI=1.5V, VOL=0.5V, VIH=3.5V, and VOH=4.4V. a. What is the lowest voltage that can be output by an inverter for a logical 1 output? Why? b. What is the highest voltage that must be interpreted by a receiver as logical 0? Why? c. What is the lowest voltage that must be interpreted by a receiver as logical 1? Why?
- Exclusive OR (XOR) and Exclusive NOR (XNOR) gates can be used a. as parity generators b. as parity checkers c. as comparators d. as controlled inverters e. as all of the given answersWith the following functions use a 4:1 multiplexer(mux) and minimum number of extra gates. Remember that to create the inverse of an input variable (i.e., A’, B’, etc.), you need to use an inverter. Hint:remember that you may need to try different variables on the select lines (i.e., A and B, or B and C, or A and C) to find the solution with the minimum number of extra gates. Implement each of the functions from from the above question using a 2:1 multiplexer(mux) and a minimumnumber of extra gates. Hint:remember that you may need to try different variables (i.e., A or B or C) on the select line to find the solutionwith the minimum number of extra gates. please explain in detail with a truth table as well as the schematics using a MUX.Consider a family of logic gates that operate under the static discipline with the following voltage thresholds: VI=1.5V, VOL=0.5V, VIH=3.5V, and VOH=4.4V. a. What is the lowest voltage that can be output by an inverter for a logical 1 output? Explain. b. What is the highest voltage that must be interpreted by a receiver as logical 0? Explain. c. What is the lowest voltage that must be interpreted by a receiver as logical 1? Explain.
- Implement the function, W using ONE 4-to-1 multiplexer and other logic gates. b) Implement the function, X using ONE 4-to-1 multiplexer and other logic gates. Implement the function, Y using TWO 4-to-1 multiplexer and other logic gates. d) Implement the function, Z using ONE 8-to-1 multiplexer and other logic gates. Table Q1 ВCD Braille A B D W Y 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A ololO6. F in the blanks in the truth table of the given digital circuit NOT Use fer NOT gate egX. Use paranthesis only for combining two logic gates OR and AND e ZOX+Y) er (Y+Z).OX+Y) You can use either XY or X.Y for AND gate. Write the letters in alphabetic orders: eg XY, not YX 1 5Logic Gates:* 7404LS (NOT)* 7408LS (AND)* 7432LS (OR)* 7400LS (NAND)* 7402LS (NOR)* 7486LS (EX-OR)Or you can use 74HCxx versions. Task 2: 4 INPUT PRIORITY ENCODERa) Write the truth table.b) Find the outputs in terms of min terms using minimal expression.c) By using K map, find the simple/simplest expression of theoutputs.d) Draw the circuit diagram. (Simulation design will be accepted.)e) Simulate the circuit & explain your results. (Please do notdesign separate simulations for each output. You should design ONEsimulation including all inputs and outputs.)
- Q4 A-Design Parallel load/Shift right 4 bit register with LD/SR signal. If LD/SR =1 then register parallel load from D3D2DIDO inputs. If LD/SR =0 then it shifts right. Use standard logic gates and D F-F.ehcu.org/pluginfile 100% 10 / 11 locations, count how many times is 0 and how many times 1 is. Questions:- 1- Write a program in assembly language to perform the following logic ci BL CL DL [5100]- 2- How we can perform the NEG and NOT instructions by using different instructions. 3- Write the following program by using different instruction or instructions for each instruction on the program. MOV AL , 00 MOV BX , FFFF XOR CL , FF NEG BYTE PTR [DI] AND CX , LGShow your solutions clearly and systematically. The D latch of Figure 1 is constructed with four NAND gates and an inverter. Consider the following three other ways for obtaining a D latch. In each case, draw the logic diagram and verify the circuit operation. D En D Next state of Q En 0X No change 10 Q = 0; reset state Q-1; set state 11 (a) Logic diagram (b) Function table. Figure 1: D Latch 2. Use NOR gates for all four gates. Inverters may be needed. Q 2