Computer Systems: A Programmer's Perspective (3rd Edition)
3rd Edition
ISBN: 9780134092669
Author: Bryant, Randal E. Bryant, David R. O'Hallaron, David R., Randal E.; O'Hallaron, Bryant/O'hallaron
Publisher: PEARSON
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Chapter 9.3, Problem 9.2PP
Program Plan Intro
Page table entries (PTEs):
A page table is a collection of page table entries. In the virtual address space, each page has a page table entries at a fixed offset.
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Problem
Question 03 (CO3) [0.5 + 0.5 = 1]: Given below are the contents of several Intel 8086 registers
and PHYSICAL memory addresses (ALL in hexadecimal):
Registers:
Memory Locations [Physical Address] = Contents
[05000] = 3300
[06000] = 4444
[07000] = 5555
[95000] = 367A
[96000] = 6666
[97000] = 10C5
DI = 3000
%3D
BX = 3000
%3D
ВР 3 С345
For the following instructions, determine the contents of AX after the each of the instruction has
been executed:
(а) MOV
(b) MOV
АХ, ВР
АХ, [ВХ+DI]
AX =
AX
Q.No.8: In paging (given
diagram), for CPU request
there are two access time one
for accessing page table and
one for physical memory
access.
physical
address f0000..0000
logical
address
CPU
a) How should we minimize
this access time? Redraw
1111...1111
the figure.
b) Formulate the formula for
Effective Access Time.
c) Calculate
Access Time (EAT) by
assuming the Hit ratio (a )
the Effective
physical
memory
85% and 95%. Cache
page table
Access Time (ɛ) is 20
microsecond and Memory
Access Time (T) is 100
microsecond.
Consider a memory system that generates 16-bits addresses and the frame size is 32-byte. At time To the status of
the page table is given below.
Page Table Entry
Page #
1911
11
561
56
644
1068
1884
52
58
42
194
46
a) What is the maximum number of entries within a single page/frame?
b) What is the maximum number of page table entries in the memory system?
c) Using the given page table, determine the physical addresses for the following logical addresses. Write down
the physical addresses in binary and decimal format.
(i)
(iii)
0101000010001011
1110101110010111
(ii)
(iv)
0001100001100111
1110111011101001
Chapter 9 Solutions
Computer Systems: A Programmer's Perspective (3rd Edition)
Ch. 9.2 - Prob. 9.1PPCh. 9.3 - Prob. 9.2PPCh. 9.6 - Prob. 9.3PPCh. 9.6 - Prob. 9.4PPCh. 9.8 - Practice Problem 9.5 (solution page 882) Write a C...Ch. 9.9 - Prob. 9.6PPCh. 9.9 - Prob. 9.7PPCh. 9.9 - Prob. 9.8PPCh. 9.9 - Prob. 9.9PPCh. 9.9 - Prob. 9.10PP
Ch. 9 - Prob. 9.11HWCh. 9 - Repeat Problem 9.11 for the following address....Ch. 9 - Repeat Problem 9.11 for the following address....Ch. 9 - Given an input file hello.txt that consists of the...Ch. 9 - Determine the block sizes and header values that...Ch. 9 - Prob. 9.16HWCh. 9 - Prob. 9.17HWCh. 9 - Prob. 9.18HWCh. 9 - Prob. 9.19HWCh. 9 - Write your own version of malloc and free, and...
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- I have a little bit problem with my late quiz for computer architecture, I get the answer from my lecturer but I still don't feel fully understand, can I ask for some help: In a computer system, the memory has 32 blocks and the cache has 8 blocks. Assume there is only one word per block with 4 bytes in one word. The reference sequence in terms of word location is 0, 2, 4, 10, 5, 12, 8, 18, 13. If the cache is direct-mapped, how many misses do we have if the cache is initially empty? Can you give the hit or miss for each reference?arrow_forward5. Suppose that a machine has 38-bit virtual addresses and 32-bit physical addresses. a) What is the main advantage of a multilevel page table over a single-level one? b) With a two-level page table, 16KB pages, and 4-byte entries, i. How many bits should be allocated for the top-level page table field? ii. How many bits should be allocated for the next level page table field?arrow_forwardPlease help with a, b, and c: Consider a virtual memory system that uses paging and a translation lookaside buffer (TLB) to cache the most recent virtual page-to-physical page translations. The following assumptions are made: The memory is byte addressable. Memory accesses are to 4-byte words. Virtual addresses are 20 bits wide. Physical addresses are 16 bits wide. The page size is 4096 bytes. The TLB is 4-way set associative with 16 total entries. The contents of the TLB and the page table for the first 32 pages are shown in the figure below: TLB Page Table Index Tag PPN Valid VPN PPN Valid VPN PPN Valid 0 03 B 1 00 7 1 10 6 0 07 6 0 01 8 0 11 7 0 28 3 1 02 9 1 12 8 0 01 F 0 03 A 1 13 3 0 1 31 0 1 04 6 0 14 D 0 12 3 0 05 3 0 15 B 0 07 E 1 06 1 0 16 9 0…arrow_forward
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